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CDP1826C Datasheet Preview

CDP1826C Datasheet

CMOS 64-Word x 8-Bit Static Random-Access Memory

No Preview Available !

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
BUSO
BUS I
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CSI
-en
V5S
I 22 Voo
2 21 AO
3 20 CS/A5
4 19 AI
5 18 A2
6 17 A3
7 16 A4
8 15 TPA
9 14 MRO
10 13 flWl!
II 12 CEO
TOP VIEW
92CS-34034
TERMINAL ASSIGNMENT
CMOS 64-Word X a-Bit Static
Random-Access Memory
Features:
• Ideal for small, low-power RAM Memory requirements
In microprocessor and microcomputer applications
• Interfaces with CDP1BOO-series microprocessors
without additional address decoding
• DaiSY chain feature to further reduce external
decoding needs
• Multiple chip-select Inputs for versatility
• Single voltage supply
• No clock or precharge reqUIred
CDP1826C
The RCA CDP1B26C IS a general-purpose, fully static, 64-
word x 8-blt random-access memory, for use In CDP1800
series or other microprocessor systems where minimum
component count and/or price performance and simplicity
in use are deSirable.
The CDP1B26C has 8 common data Input and data-output
terminals with 3-state capability for direct connection to a
standard bi-directional data bus Two chip-select Inputs-
CSl and CS2 - are provided to simplify memory-system
expansion. An additional select Pin, CS/A5, IS prOVided to
enable the CDP1826C to be selected directly from the
CDP1800 multiplexed address bus without additional latch-
Ing or decoding In an 1800 system, the CS/A5 pin can be
tied to any MA address line from the CDP1800 processor. A
TPA Input IS prOVided to latch the high-order bit of thiS
address line as a chip-select for the CDP1826C. If this
CS/A5 Input is latched high, and IfCS= 1 and CS2 =Oatthe
appropriate time In the memory cycle, the CDP1826C will
be enabled for writing or reading. In a non-1800 system, the
TPA pin can be tied high, and the CS/A5 pin can be used as
a normal address Input
The six Input-address buffers are gated with the Chip-select
function to reduce standby current when thedevlce is dese-
lected, as well as to provide for a Simplified power down
mode by reducing address buffer sensitivity to long fall
times from address drivers which are being powered down
l¢q
ADOR BUS
TPA
----
-----
AOoR BUS
TPA
NO-N2 MAo
TPB
Q
DATA )
ROM
RAM
CoPI826C
iiRD
CEO
MRO
MWR
CPU
CoPI800
SERIES
SCO SCI
INTERRUPT
oMA-IN OMA:miT
EFI-EF4
I/O CONTROL)
" "/1 a-BIT BIDIRECTIONAL DATA BUS
1/
92CM-34043
Fig 1 - TYPical CDP1802 mlcrocprocessor system
File Number 1311
_____________________________________________ 671




GE

CDP1826C Datasheet Preview

CDP1826C Datasheet

CMOS 64-Word x 8-Bit Static Random-Access Memory

No Preview Available !

••Random-A~_M.morl (RAM.) ______________________________________~
CDP1828C
Two memory control signals, MRD and MWR, are provided
for reading from and writing to the CDP1826C. The logic is
designed so that MWR overrides MRD, allowing the chip to
be controlled from a Single R/iNline
For such an Interface, the MRD line can be tied to Vss, with
the MWR line connected to R/iN.
A CHIP ENABLE OUTPUT is provided for daisy-chaining to
additional memories or 1/0 devices. This output is high
whenever the chip-select function selects the CDP1826C,
which deselects any other chip which has its CS input
connected to the CDP1826C CEO output. The connected
£!!!£.is selected when the CDP1826C is de-selected and the
MRD input is low. Thus, the CEO is only active for a read
cycle and can be set up so that a CEO of another device can
feed the MRi5 of the CDP1826C, which in turn selects a third
chip in the daisy chain.
The CDP1826C has a recommended operating voltage of
4.5 to 5.5 V and is supplied in 22-lead hermetic dual-in-line
side-brazed ceramic packages (D suffix), in 22-lead dual-
in-line plastic packages (E suffix). The CDP1826C is also
available in chip form (H suffiX).
MAXIMUM RATINGS. Absolute-MaxImum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltages referenced to Vss Terminal) .............................................................................. -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS .........................................................................-0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ..................................................................................±10 rnA
POWER DISSIPATION PER PACKAGE (Po)
For TA= -40 to + 60° C (PACKAGE TYPE E) ............................................................................ 500 mW
For TA= + 60 to + 85° C (PACKAGE TYPE E) ............................................. Derate Linearly at 12 mW/O C to 200 mW
For TA = -55 to + 100°C (PACKAGE TYPE D) ........................................................................... 500 mW
For TA= + 100 to + 125° C (PACKAGE TYPE D) .......................................... Derate Linearly at 12 mW/o C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA)
PACKAGE TYPE D .............................................................................................. -55 to +125°C
PACKAGE TYPE E ......................................................................................••.•.•... -40 to +85°C
STORAGE TEMPERATURE RANGE (T",) ......................................................................... -65 to + 150°C
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1/16 ± 1/32 Inch (1 59 ± 0 79 mm) from case for 10 s max .................................................... +265°C
RECOMMENDED OPERATING CONDITIONS at TA = Full Package Temperature Range.
For maxImum relIabIlIty, operating condItions should be selected so that operation is always within the following ranges:
CHARACTERISTIC
DC Operating Voltage Range
input Voltage Range
Input Signal Rise or Fall Time
VeD = 5 V
LIMITS
CDP1826C
MIN.
MAX,
4.5 6.5
Vss Vee
t" tf -
10
UNITS
V
lIS
872 ____________________________________________________________


Part Number CDP1826C
Description CMOS 64-Word x 8-Bit Static Random-Access Memory
Maker GE
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CDP1826C Datasheet PDF






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