CDP1802A
Features
:
- Minimum instruction fetch-execute time of 5 Il S or 7.5 Il S at VDD = 5 V;
2.51ls or 3.75 Il S at VDD = 10 V
- Any bination of standard RAM and ROM up to 65,536 bytes
- Operates with slow mem Ofles, up to 1 Il S access time at f CL = 4 MHz
- 8-bit parallel organization with bidirectional data bus and multiplexed addres S bus
- 16 x 16 matrix of registers for use as multiple program counters, data pointers, or data registers
- On-chip DMA, mterrupt, and flag inputs
- Programmable smgle-bit output port
- 91 easy-to-use instructions
The RCA-CDP1802A LSI CMOS 8-blt register-oriented central-processing unit...
