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  Fujitsu Electronic Components Datasheet  

CS101 Datasheet

Standard Cell

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FUJITSU SEMICONDUCTOR
DATA SHEET
DS06-20210-2E
Semicustom
CMOS
Standard Cell
CS101 Series
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power
consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three
types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use.
As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in
previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high-
speed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
www.DataSheet4U.com
• Technology
: 90 nm Si gate CMOS
7- to 10-metal layers.
Low-K (low permittivity) material is used for all dielectric inter-layers.
Three different types of core transistors (low leak, standard, and high speed)
can be used on the same chip.
The design rules comply with industry standard processes.
• Power supply voltage
: +1.2 V ± 0.1 V (standard)
• Operation junction temperature : 40 °C to + 125 °C (standard)
• Gate delay time
: tpd = 12 ps (1.2 V, Inverter, F/O = 1)
• Gate power consumption
: Pd = 2.7 nW/MHz/BC (1.2 V, 2 NAND, F/O = 1)
• High level of integration
: Up to 91 million gates
• Reduced chip sized realized by I/O with pad.
• Support for a wide range of cell sets (from low power versions to ultra high speed versions).
• Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorpo-
rated.
• Compiled cell (RAM, ROM, others)
• Support for ultra high speed (up to 10 Gbps) interface macros.
• Special interfaces (LVDS, SSTL2, etc.)
• Supports use of industry standard libraries (.LIB).
• Uses industry standard tools and supports the optimum tools for the application.
(Continued)


  Fujitsu Electronic Components Datasheet  

CS101 Datasheet

Standard Cell

No Preview Available !

CS101 Series
(Continued)
• Short-term development using a physical prototyping tool
• One pass design using a physical synthesis tool
• Hierarchical design environment for supporting large-scale circuits
• Support for Signal Integrity, EMI noise reduction
• Support for static timing sign-off
• Optimum package range : FBGA, FC-BGA, PBGA,TEBGA
MACRO LIBRARIES (including those in preparation)
1. Logic cells (about 400 types)
Library sets having three different types of core transistors with a different threshold value are provided.
Adder
AND
AND-OR
AND-OR Inverter
Buffer
Clock Buffer
Decoder
Delay Buffer
ENOR
EOR
Inverter
Latch
NAND
NOR
OR
OR-AND
OR-AND Inverter
SCAN Flip flop
Non-SCAN Flip Flop Selector
Others
2. IP macros
Compliance with the design rules recommended by the industry standard STARC (Semiconductor Technology
Academic Research Center) recommendations which means a wide range of commercially available IP macros
can be used.
Fujitsu plans to offer the following macros.
CPU/DSP
ARM9
DSPs for communications, AV, and similar applications, others
Multi-media processing macro JPEG, MPEG, others
Mixed signal macro
ADC, DAC, OPAMP, others
Compiled macro
RAM (1-port, 2-port), ROM, product sum calculator, others
PLL Analog PLL
3. Special I/O interface macro
Interface macro
LVDS, SSTL2, HSTL, GTL, others
Fast I/F macro
6 Gbps I/F, 10 Gbps I/F, others
2


Part Number CS101
Description Standard Cell
Maker Fujitsu Media Devices
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CS101 Datasheet PDF






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