P3041 Datasheet | Freescale Semiconductor

features : - Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC - Three levels of instructions: User, supervisor, and hypervisor - Independent boot and reset - Secure boot capability - Core Net fabric supporting coherent and non-coherent transactions amongst Core Net end-points - Core Net platform cache with ECC - Core Net bridges between the Core Net fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces - One 10-Gigabit Ethernet (XAUI) controller - Five 1-Gigabit Ethernet controllers - SGMII interfaces - 2.5 Gbps SGMII interfaces - RGMII interfaces - One 64-bit DDR3 SDRAM memory controller with ECC - Multicore programmable interrupt controller - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Two 4-channel DMA engines FC-PBGA- 1295 37.5 mm x 37.5 mm - Enhanced local bus controller (e LBC) - Four PCI Express 2.0 controllers/ports - Two serial Rapid IO® controllers/ports (s RIO port) supporting version 1.3 with features from 2.1 - Two serial ATA (SATA 2.0) controllers - Enhanced secure digital host controller (SD/MMC) - Enhanced serial peripheral interfaces (e SPI) - 2× high-speed USB 2.0 controllers with integrated PHYs © 2010- 2013 Freescale Semiconductor, Inc. All rights reserved. Table of Contents 1 2 Pin Assignments and Reset States - - - - .3 1.1 1295 FC-PBGA Ball Layout Diagrams - - . . . .3 1.2 Pinout List - - - - - - - .9 Electrical Characteristics - - - - - . . .51 2.1 Overall DC Electrical Characteristics...