P3041
Overview
- Four e500mc Power Architecture cores, each with a backside 128 KB L2 cache with ECC - Three levels of instructions: User, supervisor, and hypervisor - Independent boot and reset - Secure boot capability
- CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet end-points
- CoreNet platform cache with ECC
- CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces
- One 10-Gigabit Ethernet (XAUI) controller
- Five 1-Gigabit Ethernet controllers - SGMII interfaces - 2.5 Gbps SGMII interfaces - RGMII interfaces
- One 64-bit DDR3 SDRAM memory controller with ECC
- Multicore programmable interrupt controller
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
