— Added 8-pin dual flat no lead (DFN) packages to features list. Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages. Figure 2-1. Memory Map — Clarif.

Page Number(s) N/A 19 21 27 27 118 113 Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). Table 13-3. Interrupt Sources — Corrected vector addresses for k.

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