Description
of Change
Rev 1.0 Rev 2.0
Rev 3.0 Rev 4.0 Rev 5.0 Rev 6.0
Rev 7.0 Rev 8.0
Initial Public Release
Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO).Added “Typical Min” values to Table 10-17. Editing grammar, spelling, consistency of language throughout family.Updated values in Regulator Parameters Table 10-9; External Clock Operation Timing Requirements Table 10-13; SPI Timing Table 10-18; ADC Parameters Table 10-24; and IO Loading Coefficients at 10MHz Table 10-2
Features
- in italics are NOT available in the 56F8157 device.
- Up to 60 MIPS at 60MHz core frequency.
- DSP and MCU functionality in a unified,
C-efficient architecture.
- Access up to 4MB of off-chip program and 32MB of
data memory.
- Chip Select Logic for glueless interface to ROM and
SRAM.
- 256KB of Program Flash.
- 4KB of Program RAM.
- 8KB of Data Flash.
- 16KB of Data RAM.
- 16KB Boot Flash.
- Up to two 6-channel PWM modules.