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MC100ES6210 - Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer

General Description

The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz.

The device consists of two independent 1:5 clock fanout buffers.

The input signal of each fanout buffer is distributed to five identical, differential ECL/PECL outputs.

Key Features

  • Dual 1:5 differential clock distribution 30 ps maximum device skew Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V,.
  • 3.3 V, 2.5 V or.
  • 2.5 V suppl.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Freescale Semiconductor Technical Data MC100ES6210 Rev 3, 02/2005 www.DataSheet4U.com Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer The MC100ES6210 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6210 supports various applications that require to distribute precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low clock skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.