MC100ES6210
Key Features
- Dual 1:5 differential clock distribution 30 ps maximum device skew Fully differential architecture from input to all outputs SiGe technology supports near-zero output skew Supports DC to 3 GHz operation of clock or data signals ECL/PECL patible differential clock outputs ECL/PECL patible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 32 lead LQFP package Industrial temperature range Pin and function patible to the MC100EP210 32-lead Pb-free Package Available
