MC100ES6039 chip equivalent, 3.3v ecl/pecl/hstl/lvds generation chip.
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* Maximum Frequency >1.0 GHz Typical 50 ps Output-to-Output Skew PECL Mode Operating Range: VCC = 3.135 V to 3.8.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The .
Pin CLK(1), CLK(1) EN(1) MR(1)
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ECL Diff Clock Inputs ECL Sync Enable ECL Master Reset ECL Reference Output ECL Diff ÷2/4 Outputs ECL Diff ÷4/6 Outputs ECL Freq. Select Input ÷2/4 ECL Freq. Select Input ÷4/6 ECL Positive .
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