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DSP56367 - 24-Bit Audio Digital Signal Processor

Description

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Packaging

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1-1 2-1 3-1 4-1 5-1 A-1 This document briefly describes t

Features

  • Core features are described fully in the DSP56300 Family Manual. 1.2.
  • DSP56300 modular chassis 150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal logic supply (QVCCL) of 1.8V. 100 Million Instructions Per Second (MIPS) with a 100 MHz clock at internal logic supply (QVCCL) of 1.5V. Object Code Compatible with the 56K core. Data ALU with a 24 × 24 bit multiplier-.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Freescale Semiconductor Data Sheet: Technical Data Document Number: DSP56367 Rev. 2.1, 1/2007 DSP56367 24-Bit Audio Digital Signal Processor 1 Overview Contents 1 2 3 4 5 A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal/Connection Descriptions . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . . . . . Power Consumption Benchmark . . . . . . . . . . 1-1 2-1 3-1 4-1 5-1 A-1 This document briefly describes the DSP56367 24-bit digital signal processor (DSP). The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs.
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