P18N50 Datasheet | Fairchild Semiconductor

Features - 18A, 500V, RDS(on) = 0.265Ω @VGS = 10 V - Low gate charge ( typical 45 n C) - Low Crss ( typical 25 p F) - Fast switching - 100% avalanche tested - Improved dv/dt capability Uni FET Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and mutation mode. These devices are well suited for high efficient switched mode power supplies and active power factor correction. ..net G G DS TO-220 FDP Series GD S TO-220F FDPF Series Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL Drain-Source Voltage Drain Current Drain Current Gate-Source voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) - Derate above 25°C (Note 2) (Note 1) (Note 1) (Note 3) Parameter - Continuous (TC = 25°C) - Continuous (TC = 100°C) - Pulsed (Note 1) FDP18N50 500 18 10.8 72 ±30 945 18 FDPF18N50 - 10.8 ∗ 72 ∗ Unit V A A A V m J A m J V/ns 23.5 4.5 235 1.88 -55 to +150 300 38.5 0.3 W W/°C °C °C Operating and Storage Temperature Range Maximum Lead Temperature for Soldering Purpose, 1/8” from Case for 5...