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MM74C574 - 3-STATE Octal D-Type Edge-Triggered Flip-Flop

Download the MM74C574 datasheet PDF. This datasheet also covers the MM74C574MTC variant, as both devices belong to the same 3-state octal d-type edge-triggered flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology.

They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MM74C574MTC_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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MM74C02 Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverter Fairchild
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Other Datasheets by Fairchild (onsemi)

Part Number Description
MM74C193 Synchronous 4-Bit Up/Down Binary Counter
MM74C244 Inverting - Non-Inverting Octal Buffer and Line Driver
MM74C374 3-STATE Octal D-Type Flip-Flop
MM74C76 Dual J-K Flip-Flops
MM74C902 Hex Non-Inverting TTL Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop September 1983 Revised February 1999 MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. These devices are positive edge triggered flip-flops. Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input.