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FM24C04U - 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Download the FM24C04U datasheet PDF. This datasheet also covers the FM2 variant, as both devices belong to the same 4k-bit standard 2-wire bus interface serial eeprom family and are provided as variant models within a single manufacturer datasheet.

General Description

The FM24C04U/05U devices are 4096 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the Standard IIC 2-wire protocol.

They are designed to minimize device pin count and simplify PC board layout requirements.

Key Features

  • I Extended operating voltage 2.7V.
  • 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I IIC compatible interface.
  • Provides bi-directional data transfer protocol I Sixteen byte page write mode.
  • Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper half (FM24C05U only) I End.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (FM2-4C04.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM August 2000 FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description The FM24C04U/05U devices are 4096 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol. They are designed to minimize device pin count and simplify PC board layout requirements. The upper half (upper 2Kbit) of the memory of the FM24C05U can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).