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FIN1026 - 3.3V LVDS 2-Bit High Speed Differential Receiver

General Description

This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology.

The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels.

LVDS provides low EMI at ultra low power dissipation even at high frequencies.

Overview

FIN1026 3.3V LVDS 2-Bit High Speed Differential Receiver June 2002 Revised June 2002 FIN1026 3.

Key Features

  • s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 2.5ns maximum propagation delay s Low power dissipation s Power-Off protection s Fail safe protection for open-circuit, shorted and terminated non-driven input conditions s Meets or exceeds the TIA/EIA-644 LVDS standard s 14-Lead TSSOP package saves space Ordering Code: Order Number FIN1026MTC Package Number MTC14 Package.