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FIN1002 - LVDS 1-Bit High Speed Differential Receiver

Download the FIN1002 datasheet PDF. This datasheet also covers the FIN variant, as both devices belong to the same lvds 1-bit high speed differential receiver family and are provided as variant models within a single manufacturer datasheet.

General Description

This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology.

The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.

Key Features

  • s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum pulse skew s 2.5ns maximum propagation delay s Bus pin ESD (HBM) protection exceeds 10kV s Power-Off over voltage tolerant input and output s Fail safe protection for open-circuit and non-driven, shorted or terminated conditions s High impedance output at VCC < 1.5V s Meets or exceeds the TIA/EIA-644 LVDS standard s 5-Lead SOT23 package saves space Ordering Code: Order Number FIN1002M5 FIN1002M5X Package Number MA05B.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (FIN-1002.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
FIN1002 High-Speed Differential Reciever ON Semiconductor
FIN1001 High-Speed Differential Driver ON Semiconductor
FIN1019 3.3V LVDS High Speed Differential Driver/Receiver ON Semiconductor
FinePix S5100 Manual Fujifilm
FinePix S5500 Manual Fujifilm

Other Datasheets by Fairchild (onsemi)

Part Number Description
FIN1001 3.3V LVDS 1-Bit High Speed Differential Driver
FIN1017 3.3V LVDS 1-Bit High Speed Differential Driver
FIN1018 3.3V LVDS 1-Bit High Speed Differential Receiver
FIN1019 3.3V LVDS High Speed Differential Driver/Receiver
FIN1022 2 X 2 LVDS High Speed Crosspoint Switch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
FIN1002 LVDS 1-Bit High Speed Differential Receiver February 2002 Revised February 2002 FIN1002 LVDS 1-Bit High Speed Differential Receiver General Description This single receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock or data. The FIN1002 can be paired with its companion driver, the FIN1001, or with any other LVDS driver. Features s Greater than 400Mbs data rate s 3.3V power supply operation s 0.4ns maximum pulse skew s 2.