FDP603AL / FDB603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low
voltage applications such as DC/DC converters and high
efficiency switching circuits where fast switching, low in-line
power loss, and resistance to transients are needed.
Critical DC electrical parameters specified at elevated
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low RDS(ON).
175°C maximum junction temperature rating.
Absolute Maximum Ratings TC = 25°C unless otherwise noted
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
PD Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
RθJC Thermal Resistance, Junction-to-Case
RθJA Thermal Resistance, Junction-to-Ambient
-65 to 175
© 1998 Fairchild Semiconductor Corporation