FDG6321C
Description
These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.
Key Features
- N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 Ω @ VGS= 4.5V
- RDS(ON) = 0.60 Ω @ VGS= 2.7 V
- P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 Ω @ VGS= -4.5V
- RDS(ON) = 1.5 Ω @ VGS= -2.7V
- Very small package outline SC70-6
- Very low level gate drive requirements allowing direct operation in 3 V circuits(VGS(th) < 1.5 V)
- Gate-Source Zener for ESD ruggedness (>6kV Human Body Model)
