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FDG314P - Digital FET/ P-Channel

Description

This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor’s proprietary, high cell density, DMOS technology.

This very high density process is tailored to minimize onstate resistance at low gate drive conditions.

Features

  • -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS = -2.7 V.
  • Very low gate drive requirements allowing direct operation in 3V cirucuits (VGS(th) 6 kV Human Body Model). Compact industry standard SC70-6 surface mount package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FDG314P July 2000 FDG314P Digital FET, P-Channel General Description This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize onstate resistance at low gate drive conditions. This device is designed especially for battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. Features • -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS = -2.7 V. • • • Very low gate drive requirements allowing direct operation in 3V cirucuits (VGS(th) <1.5 V). Gate-Source Zener for ESD ruggedness (>6 kV Human Body Model).
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