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DM74LS156 - Dual 2-Line to 4-Line Decoders/Demultiplexers

Download the DM74LS156 datasheet PDF. This datasheet also covers the DM74LS155 variant, as both devices belong to the same dual 2-line to 4-line decoders/demultiplexers family and are provided as variant models within a single manufacturer datasheet.

General Description

These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package.

Key Features

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📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM74LS155_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers National Semiconductor
DM74LS151 Data Selector/Multiplexer National Semiconductor
DM74LS153 Dual 4-Line to 1-Line Data Selectors/Multiplexers National Semiconductor
DM74LS154 4-Line to 16-Line Decoders/Demultiplexers National Semiconductor
DM74LS155 Dual 2-Line to 4-Line Decoders/Demultiplexers National Semiconductor

Other Datasheets by Fairchild (now onsemi)

Part Number Description
DM74LS151 1-of-8 Line Data Selector/Multiplexer
DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers
DM74LS154 4-Line to 16-Line Decoder/Demultiplexer
DM74LS155 Dual 2-Line to 4-Line Decoders/Demultiplexers
DM74LS157 Quad 2-Line to 1-Line Data Selectors/Multiplexers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74LS155 • DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers August 1986 Revised April 2000 DM74LS155 • DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs.