DM74AS640 Datasheet | Fairchild Semiconductor

DM74AS640 3-STATE Octal Bus Transceiver October 1986 Revised March 2000 DM74AS640 3-STATE Octal Bus Transceiver General Description This advanced Schottky device contains 8 pairs of 3STATE logic elements configured as octal bus transceiver. This circuit is designed for use in memory, microprocessor systems and in asynchronous bidirectional data buses. This device transmits data from the A bus to the B bus, or vice versa, depending upon the logic level of the direction control input (DIR). The enable input (G) can be used to disable the devices, effecting isolation of buses A and B. The 3-STATE circuitry also contains a protection feature that prevents these transceivers from glitching the bus during power-up or power-down. Features s Switching specifications at 50 p F s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin patible with Schottky, low power Schottky, and advanced low power Schottky TTL counterpart s Improved AC performance over Schottky, low power Schottky, and advanced low power Schottky counterparts s 3-STATE outputs independently controlled on A and B buses s Low output impedance drive to drive terminated transmission lines to 133Ω s Specified to interface with CMOS at VOH = VCC - 2V Ordering Code: Order Number DM74AS640WM DM74AS640N Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Control Inputs Operation G L L H H = HIGH Logic Level L = LOW Logic Level X = Immaterial DIR L H X B Data to A Bus A Data to B Bus Isolation Logic Diagram Top View © 2000 Fairchild Semiconductor Corporation DS006708 .fairchildsemi....