Datasheet4U Logo Datasheet4U.com

DM74ALS151 - 1 of 8 Line Data Selector/Multiplexer

Description

This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs.

Two complementary outputs provide both inverting and non-inverting buffer operation.

Features

  • to ensure that select input changes do not cause invalid output transients. Features s Advanced oxide-isolated, ion-implanted Schottky TTL process s Switching performance is guaranteed over full temperature and VCC supply range s Pin and functional compatible with LS family counterpart s Improved output transient handling capability Ordering Code: Order Number DM74ALS151M DM74ALS151N Package Number M16A N16E Package.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DM74ALS151 1 of 8 Line Data Selector/Multiplexer National Semiconductor
DM74ALS1011A Triple 3 Input AND Buffer National
DM74ALS1242 Quad Bidirectional Bus Drivers National Semiconductor
DM74ALS1242A Quad Bidirectional Bus Driver National
DM74ALS132 DM74ALS132 Quad 2-Input NAND Gate with Schmitt Trigger Inputs National Semiconductor

Other Datasheets by Fairchild (onsemi)

Part Number Description
DM74ALS153 Dual 1-of-4 Line Data Selector/Multiplexer
DM74ALS157 Quad 1-of-2 Line Data Selector/Multiplexer
DM74ALS158 Quad 1-of-2 Line Data Selector/Multiplexer
DM74ALS1000A Quadruple 2-Input NAND Buffer
DM74ALS1004 Hex Inverting Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74ALS151 1 of 8 Line Data Selector/Multiplexer April 1984 Revised February 2000 DM74ALS151 1 of 8 Line Data Selector/Multiplexer General Description This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the LOW state and the W output to the HIGH state. The Select input buffers incorporate internal overlap features to ensure that select input changes do not cause invalid output transients.