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CD4027BCN, CD4027BC Datasheet - Fairchild Semiconductor

CD4027BCN Dual J-K Master/Slave Flip-Flop

The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the cloc.

CD4027BCN Features

* s Wide supply voltage range: s High noise immunity: 3.0V to 15V 0.45 VDD (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS s Low power: 50 nW (typ.) s Medium speed operation: 12 MHz (typ.) with 10V supply Ordering Code: Order Number CD4027BCM CD4027BCN Package Number

CD4027BC-FairchildSemiconductor.pdf

This datasheet PDF includes multiple part numbers: CD4027BCN, CD4027BC. Please refer to the document for exact specifications by model.
CD4027BCN Datasheet Preview Page 2 CD4027BCN Datasheet Preview Page 3

Datasheet Details

Part number:

CD4027BCN, CD4027BC

Manufacturer:

Fairchild Semiconductor

File Size:

56.43 KB

Description:

Dual j-k master/slave flip-flop.

Note:

This datasheet PDF includes multiple part numbers: CD4027BCN, CD4027BC.
Please refer to the document for exact specifications by model.

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TAGS

CD4027BCN CD4027BC Dual J-K Master Slave Flip-Flop Fairchild Semiconductor

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