74VCX16841 Datasheet | Fairchild Semiconductor

Description The VCX16841 contains twenty non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX16841 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O patibility up to 3.6V. The 74VCX16841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V- 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s t PD (Dn to On) 3.0 ns max for 3.0V to 3.6V VCC 3.4 ns max for 2.3V to 2.7V VCC 6.8 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Static Drive (IOH/IOL) ±24 m A @ 3.0V VCC ±18 m A @ 2.3V VCC ±6 m A @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 m A s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX16841MTD Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn LEn D0- D19 O0- O19 Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs © 1999 Fairchild Semiconductor Corporation DS500132.prf .fairchildsemi. Connection Diagram Truth Tables Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H...