74VCX16601 Datasheet | Fairchild Semiconductor

74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 Revised April 1999 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The VCX16601 is an 18-bit universal bus transceiver which bines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-to LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. Features s 1.65V- 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s t PD (A to B, B to A) 2.9 ns max for 3.0V to 3.6V VCC 3.5 ns max for 2.3V to 2.7V VCC 7.0 ns max for 1.65V 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Static Drive (IOH/IOL) ±24 m A @ 3.0V VCC ±18 m A @ 2.3V VCC ±6 m A @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 m A The VCX16601 is designed for low voltage (1.65V to 3.6V) s ESD performance: VCC applications with I/O capability up to 3.6V. .. Human body model > 2000V The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain Machine model >200V ing low CMOS power dissipation. Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up...