74LVX3245 Datasheet | Fairchild Semiconductor

Features - Bidirectional Interface Between 3 V and 5 V Buses - Inputs patible with TTL Level - 3 V Data Flow at A-Port and 5 V Data Flow at B- Port - Outputs Source / Sink: 24 m A - Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance - Implements Proprietary EMI Reduction Circuitry - Functionally patible with the 74 Series 245 Description The 74LVX3245 is a dual-supply, 8-bit translating transceiver designed to interface between a 3 V bus and a 5 V bus in a mixed 5 V supply environment. The Transmit/ Receive (T/R¯ ) input determines the direction of data flow. Transmit (active-HIGH) enables data from A-ports to B-ports; receive (active-LOW) enables data from B-ports to A-ports. The output enable input, when HIGH, disables both A- and B-ports by placing them in a high-impedance condition. The A-port interfaces with the 3 V bus; the B-port interfaces with the 5 V bus. The 74LVX3245 is suitable for mixed-voltage applications, such as notebook puters using 3.3 V CPU and 5V peripheral ponents. Related Resources - AN-5001 - Using Fairchild’s LVX Low-Voltage Dual-Supply CMOS Translating Transceivers Ordering Information Part Number Operating Temperature Range Package 74LVX3245QSC 74LVX3245QSCX 74LVX3245MTC 74LVX3245MTCX -40 to +85°C 24-Lead Quarter-Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 24-Lead Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide Packing Method Tubes Tape and Reel Tubes Tape and Reel © 1993 Fairchild Semiconductor Corporation 74LVX3245 - Rev. 1.6 .fairchildsemi. - 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs Logic Symbol Pin Configuration Figure 1. Logic Symbol Figure 2. Pin Configuration Pin Definitions Pin # 1 2 3, 4, 5, 6, 7, 8, 9, 10 11, 12, 13 14, 15, 16, 17, 18,...