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Fairchild Semiconductor Electronic Components Datasheet

74LVQ00 Datasheet

Low Voltage Quad 2-Input NAND Gate

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November 1997
74LVQ00
Low Voltage Quad 2-Input NAND Gate
General Description
The LVQ00 contains four 2-input NAND gates.
Features
n Ideal for low power/low noise 3.3V applications
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Guaranteed pin-to-pin skew AC performance
n Guaranteed incident wave switching into 75
Ordering Code: See
Order Number
74LVQ00SC
74LVQ00SJ
Package Number
M14A
M14D
Package Description
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC
14-Lead Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Assignment for
for SOIC JEDEC and EIAJ
Pin Descriptions
DS011341-1
Pin Names
An, Bn
On
Description
Inputs
Outputs
DS011341-2
© 1997 Fairchild Semiconductor Corporation DS011341
PrintDate=1997/11/10 PrintTime=09:36:39 23554 ds011341 Rev. No. 4 cmserv Proof
www.fairchildsemi.com
1
1


Fairchild Semiconductor Electronic Components Datasheet

74LVQ00 Datasheet

Low Voltage Quad 2-Input NAND Gate

No Preview Available !

Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
±200 mA
−65˚C to +150˚C
±100 mA
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
LVQ
2.0V to 3.6V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
74LVQ
0V to VCC
0V to VCC
−40˚C to +85˚C
Minimum Input Edge Rate (V/t)
VIN from 0.8V to 2.0V
VCC @ 3.0V
125 mV/ns
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for ac-
tual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum High Level
Input Voltage
VIL Maximum Low Level
Input Voltage
VOH Minimum High Level
Output Voltage
VOL Maximum Low Level
Output Voltage
IIN
IOLD
IOHD
ICC
VOLP
VOLV
VIHD
VILD
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(Note 4)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
VCC TA = +25˚C
(V)
TA =
−40˚C to +85˚C
Typ Guaranteed Limits
3.0 1.5
2.0
2.0
3.0 1.5
0.8
0.8
3.0 2.99
3.0
2.9
2.58
2.9
2.48
3.0 0.002
3.0
0.1
0.36
0.1
0.44
3.6
3.6
3.6
3.6
3.3 0.6
3.3 −0.5
3.3 1.5
3.3 1.5
±0.1
2.0
1.0
−1.0
2.0
0.8
±1.0
36
−25
20.0
Units
Conditions
V VOUT = 0.1V
or VCC − 0.1V
V VOUT = 0.1V
or VCC − 0.1V
V IOUT = −50 µA
V VIN = VIL or VIH
IOH = −12 mA
(Note 3)
V IOUT = 50 µA
V VIN = VIL or VIH
IOL = 12 mA
(Note 3)
µA VI = VCC, GND
mA VOLD = 0.8V Max
(Note 5)
mA VOHD = 2.0V Min (Note
5)
µA VIN = VCC
or GND
V (Notes 6, 7)
V (Notes 6, 7)
V (Notes 6, 8)
V (Notes 6, 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD),
f = 1 MHz.
www.fairchildsemi.com
2
PrintDate=1997/11/10 PrintTime=09:36:41 23554 ds011341 Rev. No. 4 cmserv Proof
2


Part Number 74LVQ00
Description Low Voltage Quad 2-Input NAND Gate
Maker Fairchild Semiconductor
Total Page 6 Pages
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