Revised February 2000
4-to-16 Line Decoder with Latch
The MM74HC4514 utilizes advanced silicon-gate CMOS
technology, which is well suited to memory address decod-
ing or data routing application. It possesses high noise
immunity and low power dissipation usually associated with
CMOS circuitry, yet speeds comparable to low power
Schottky TTL circuits. It can drive up to 10 LS-TTL loads.
The MM74HC4514 contain a 4-to-16 line decoder and a 4-
bit latch. The latch can store the data on the select inputs,
thus allowing a selected output to remain HIGH even
though the select data has changed. When the LATCH
ENABLE input to the latches is HIGH the outputs will
change with the inputs. When LATCH ENABLE goes LOW
the data on the select inputs is stored in the latches. The
four select inputs determine which output will go HIGH pro-
vided the INHIBIT input is LOW. If the INHIBIT input is
HIGH all outputs are held LOW thus disabling the decoder.
The MM74HC4514 is functionally and pinout equivalent to
the CD4514BC and the MC1451BC. All inputs are pro-
tected against damage due to static discharge diodes from
VCC and ground.
s Typical propagation delay: 18 ns
s Low quiescent power: 80 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads (74HC Series)
Order Number Package Number
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-0013, 0.300” Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS005215