74C85 Datasheet | Fairchild Semiconductor

Description The MM74C85 is a four-bit magnitude parator which will perform parison of straight binary or BCD codes. The circuit consists of eight paring inputs (A0, A1, A2, A3, B0, B1, B2, B3), three cascading inputs (A > B, A < B and A = B), and three outputs (A > B, A < B and A = B). This device pares two four-bit words (A and B) and determines whether they are “greater than,” “less than,” or “equal to” each other by a high level on the appropriate output. For words greater than four-bits, units can be cascaded by connecting the outputs (A > B, A < B, and A = B) of the least significant stage to the cascade inputs (A > B, A < B and A = B) of the next-significant stage. In addition the least significant stage must have a high level voltage (VIN(1)) applied to the A = B input and low level voltage (VIN(0)) applied to A > B and A < B inputs. Features s Wide supply voltage range: 3.0V to 15V s Guaranteed noise margin: 1.0V s High noise immunity: 0.4 VCC (typ.) s Low power: TTL patibility: fan out of 2 driving 74L s Expandable to 'N' stages s Applicable to binary or BCD s Low power pinout: 74L85 Ordering Code: Order Number Package Number Package Description MM74C85N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Top View © 2002 Fairchild Semiconductor Corporation DS005886 .fairchildsemi. MM74C85 Truth Table paring Inputs A3, B3 A2, B2 A1, B1 A3 > B3 A3 < B3 A3 = B3 A2 > B2 A3 = B3 A2 < B2 A3 = B3 A2 = B2 A1 > B1 A3 = B3 A2 = B2 A1 < B1 A3 = B3 A2 = B2 A1 = B1 A3 = B3 A2 = B2 A1 = B1 A3 = B3 A2 = B2 A1 = B1 A3 = B3 A2 = B2 A1 = B1 A3 =...