* Embedded processor core
* 16 bit Harvard architecture
* Two full-speed or low-speed USB 2.0 interfaces capable of host or slave functions
* 256kbytes o.

Flash and RAM memory have been increased providing larger user areas of memory for the designer to incorporate his own .

of each function please refer to Section 4. UART XTOUT XTIN Oscillator/ PLL PWMs FIFO Interface SPI Master Flash Programmer Debugger SPI Slave 1 Program Memory Bus Internal Clocks and Timers 256K Bytes E-FLASH (64K x 32) Embedded CPU Periphe.

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