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N & P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH
P‐CH
BVDSS
100V
‐100V
RDSON (MAX.)
150mΩ 250mΩ
ID
3A
‐2.5A
EMBA5C10G
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
VGS
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
ID IDM PD Tj, Tstg
LIMITS
N‐CH
P‐CH
±20
±20
3
‐2.5
2.1
‐1.8
12
‐10
2
0.8 ‐55 to 150
UNIT V
A W °C
THERMAL RESISTANCE RATINGS THERMAL RESISTANCE
SYMBOL
Junction‐to‐Case
RJC
Junction‐to‐Ambient3
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1％ 362.
EMBA5C10G Datasheet
