EUP7998 regulator equivalent, sink/source ddr termination regulator.
z z z z z z z z z z z VLDOIN Input Voltage Range: 1.1V to 3.5V VIN Input Voltage Range: 2.375V to 5.5V Typically 3 × 10μF MLCCs stable for DDR Fast Load-Transient Respons.
Power-Good Window Comparator With Soft Start, UVLO and OCP Thermal Shutdown Available in 10-Pin 3mm × 3mm TDFN and SOP-8.
The EUP7998 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The EUP7998 maintains a fas.
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