EM6GE16EWXC dram equivalent, 256m x 16 bit ddr3 synchronous dram.
* JEDEC Standard Compliant
* Power supplies: VDD & VDDQ = +1.5V ± 0.075V
* Operating temperature: 0~95°C (TC)
* Supports JEDEC clock jitter specification .
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchr.
Table 3. Ball Descriptions
Symbol CK, CK# Type Input Description
EM6GE16EWXC
Differential Clock: CK and CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output.
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