* JEDEC Standard VDD/VDDQ = 1.35V(1.283-1.45V)
* All inputs and outputs are compatible with SSTL_15 interface.
* Fully differential clock inputs (CK, /CK) ope.

EM47FM0888SBA

EM47CM1688SBB

EM47DM0888SBA

EM47EM0888SBA

EM47EM1688MBB

EM47EM1688SBB

EM47EM1688SBC

EM47EM3288MBA

EM47EM3288SBA

EM4

EM4022

EM4025

EM4026

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