EM44CM1688LBA sdram equivalent, 1gb double data rate-2 sdram.
Description
* JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
* All inputs and outputs are compatible with SSTL_18 interface.
* Fully differential clock inputs (CK,/CK.
* JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
* All inputs and outputs are compatible with SSTL_18 interface.
* Fully differential clock inputs (CK,/CK) operation.
* 8 Banks
* Posted CAS
* Burst Length: 4 and 8.
* Programmable C.
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