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Eon Silicon Solution

EN71SN10F Datasheet Preview

EN71SN10F Datasheet

1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip

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EN71SN10F
EN71SN10F
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
Multi-Chip Package
- NAND Flash Density: 1-Gbits
- Mobile DDR SDRAM Density: 512-Mbit
Device Packaging
- 107 balls FBGA
Area: 10.5x13 mm; Height: 1.2 mm
Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
Operating Temperature :-25 °C to +85 °C
NAND FLASH
Voltage Supply: 1.8V (1.7V ~ 1.95V )
Organization
- Memory Cell Array :
(128M + 4M) x 8bit for 1Gb
- Multiplexed address/ data
- Data Register : (2K + 64) x 8bit
Automatic Program and Erase
- Page Program : (2K + 64) bytes
- Block Erase : (128K + 4K) bytes
Page Read Operation
- Page Size : (2K + 64) bytes
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
Reliable CMOS Floating-Gate Technology
Endurance:
- 100K Program/Erase Cycles (with 1 bit/528
bytes ECC)
- Data Retention: 10 Years
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
NOP: 4 cycles
Cache Program/Read Operation
Copy-Back Operation
EDO mode
OTP Operation
Mobile DDR SDRAM
Density: 512M bits
Organization: 8M words x16 bits x 4 banks
Power supply: VDD/VDDQ= 1.70~1.95V
Speed: 400Mbps (max.) for data rate
2KB page size
- Row address: A0 to A12
- Column address: A0 to A9
Four internal banks for concurrent operation
Interface: LVCMOS
Burst Length : 2, 4, 8, or 16
Burst Type : Sequential and Interleave
CAS# Latency (CL) : 3
Precharge: auto precharge option for each
burst access
Drive Strength: normal, 1/2, 1/4, 1/8
Refresh: auto Refresh and self-refresh
Refresh cycles: 8192 cycles/64ms
Optional Partial Array Self Refresh (PASR)
Auto Temperature Compensated Self Refresh
(ATCSR) by built-in temperature sensor
Deep Power Down Mode
Burst termination by burst stop command and
precharge command
DLL in not implemented
Double-data-rate architecture, two data access
per clock cycle
The high-speed data transfer is realized by the
2 bits prefetch pipelined architecture
Bidirectional data strobe (DQS) is transmitted
/received with data for capturing data at the
receiver
DQS edge-aligned with data for READs;
center-aligned with data for WRITEs
Differential clock inputs (CLK and CLK# )
Commands entered on each positive CLK edge;
data and data mask referenced to both edges
of DQS
Data mask (DM) for write data
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07




Eon Silicon Solution

EN71SN10F Datasheet Preview

EN71SN10F Datasheet

1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip

No Preview Available !

Ordering Information
EN71SN10F
Product ID
NAND Flash
Configuration
EN71SN10F-45CFWP
1Gb
(128M X 8 bits)
Mobile DDR SDRAM
Speed Configuration Speed
Package
Operation
Temperature
Range
45ns
512Mb (4 Banks
X 8M X 16 bits)
200MHz
107 ball FBGA Wireless
MCP Block Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2012 Eon Silicon Solution, Inc., www.eonssi.com
Rev. A, Issue Date: 2012/12/07


Part Number EN71SN10F
Description 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip
Maker Eon Silicon Solution
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