EM620FU8B Datasheet | Emerging Memory - Logic Solutions

FEATURES - Process Technology : 0.15µm Full CMOS - Organization :256K x8 - Power Supply Voltage => EM620FU8B : 2.7~3.3V - Low Data Retention Voltage : 1.5V - Three state output and TTL patible - Packaged product designed for 45/55/70ns GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/Al Cu/Ti N/ARC Si ON/Si O2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/p NIT/PIQ) : 5.4K Angstroms - Wafer diameter : 8 inch Low Power, 256Kx8 SRAM .. EM620FU8B (Dual C/S) + (0.0) EMLSI LOGO 28 y PAD DESCRIPTIONS Name CS1,CS2 OE WE A0~A17 I/O0~I/O7 Function Chip select inputs Output Enable input Write Enable input Address Inputs Data Inputs/Outputs Name Vcc Vss NC Function Power Supply x Pre-charge Circuit Row Select Ground No Connection A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC VSS Memory Array 1024 x 2048 I/O0 ~ I/O7 Data Cont I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 A17 WE OE CS1 CS2 Control Logic BONDING INSTRUCTIONS The 2M full CMOS SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI remends using a bond wire on back side of die onto Vss bond pad for improved noise immunity. ABSOLUTE MAXIMUM RATINGS - Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating...