EDS2532JEBH-6B - 256M bits SDRAM

Features

• ×32 organization.
• Single pulsed /RAS.
• Burst read/write operation and burst read/single write operation capability.
• Byte control by DQM (Top view) A0 to A11 BA0, BA1 DQ0 to DQ31 /CS /RAS /CAS /WE DQM0 to DQM3 CKE CLK VDD VSS VDDQ VSSQ NC Address inputs Bank select address Data-input/output Chip select Row address strobe Column address strobe Write enable DQ mask enable Clock enable Clock input Power for internal circuit Ground for internal circuit Power for D.