EDD1208ALTA dram equivalent, 128 m-bit synchronous dram.
* Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
* Double Data Rate interface
Differential CLK (/C.
The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic
random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.
The synchronous DRAMs use Double Data R.
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