Description
Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In
2 2
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Function Address input Row address Column address Auto precharge
Features
- Double-data-rate architecture; two data transfers per clock cycle.
- The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
- Differential clock inputs (CK and /CK).
- DLL aligns DQ and DQS transitions with CK transi.
EBE41AE4ABHA Datasheet
