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EBE21AE8ACWA - 2GB Registered DDR2 SDRAM DIMM

Datasheet Summary

Description

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 DM0 to DM8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In 2 2 www.DataSheet4U.com Function Address input Row address Column address Auto

Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

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Datasheet Details

Part number EBE21AE8ACWA
Manufacturer Elpida Memory
File Size 272.36 KB
Description 2GB Registered DDR2 SDRAM DIMM
Datasheet download datasheet EBE21AE8ACWA Datasheet
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DATA SHEET www.DataSheet4U.com 2GB Registered DDR2 SDRAM DIMM EBE21AE8ACWA (256M words × 72 bits, 2 Ranks) Specifications • Density: 2GB • Organization  256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.0mm  Lead pitch: 1.0mm  Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.
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