EBE10UE8AEFB dimm equivalent, 1gb unbuffered ddr2 sdram dimm.
* Double-data-rate architecture; two data transfers per clock cycle
* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
*.
Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0 CKE0 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0 NC Function Address input Row address Column address Auto precha.
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