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UT54ACTS273 Datasheet Preview

UT54ACTS273 Datasheet

Octal D-Flip-Flops

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UT54ACS273/UT54ACTS273
Radiation-Hardened
Octal D-Flip-Flops with Clear
FEATURES
Contains eight flip-flops with single-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
www.DataSheetA4Up.pcloimcations include:
- Buffer/storage registers, shift registers, and pattern
generators
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
DESCRIPTION
The UT54ACS273 and the UT54ACTS273 are positive-edge-
triggered D-type flip-flops with a direct clear input.
Information at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse. When the clock input is at either the high or low
level, the D input signal has no effect at the output.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
CLK
Dx
Qx
LXX
HH
L
H
H LL
H L X No change
PINOUTS
20-Pin DIP
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
20-Lead Flatpack
Top View
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
LOGIC SYMBOL
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
(1)
CLR
(11)
CLK
1D (3)
(4)
2D
3D (7)
(8)
4D
5D (13)
(14)
6D
7D (17)
(18)
8D
R
C1
1D
(2)
1Q
(5)
2Q
(6)
3Q
(9)
4Q
(12)
5Q
(15)
(16) 6Q
7Q
(19)
8Q
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
189 RadHard MSI Logic




ETC

UT54ACTS273 Datasheet Preview

UT54ACTS273 Datasheet

Octal D-Flip-Flops

No Preview Available !

UT54ACS273/UT54ACTS273
LOGIC DIAGRAM
CLK (11)
CLR (1)
www.DataSheet4U.com
1D
(3)
2D
(4)
3D
(7)
4D
(8)
5D
(13)
6D
(14)
7D
(17)
8D
(18)
DDDDDDDD
CCCCCCCC
RRRRRRRR
(2)
1Q
(5)
2Q
(6)
3Q
(9)
4Q
(12)
5Q
(15)
6Q
(16)
7Q
(19)
8Q
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
Total Dose
SEU Threshold 2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
VI/O
TSTG
TJ
TLS
JC
II
PD
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
-0.3 to 7.0
-.3 to VDD +.3
-65 to +150
+175
+300
20
10
1
V
V
C
C
C
C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RadHard MSI Logic
190


Part Number UT54ACTS273
Description Octal D-Flip-Flops
Maker ETC
Total Page 6 Pages
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