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STK20C04 Datasheet Preview

STK20C04 Datasheet

CMOS nvSRAM High Performance 512 x 8 Nonvolatile Static RAM

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STK20C04
STK20C04
CMOS nvSRAM
High Performance
512 x 8 Nonvolatile Static RAM
FEATURES
• 30, 35 and 45ns Access Times
• 15, 20 and 25ns Output Enable Access
• Unlimited Read and Write to SRAM
• Hardware STORE Initiation
• Automatic STORE Timing
• 105 STORE cycles to EEPROM
• 10 year data retention in EEPROM
• Automatic RECALL on Power Up
• Hardware RECALL Initiation
• Unlimited RECALL cycles from EEPROM
• Single 5V±10% Operation
• Commercial and Industrial Temperatures
• Available in 600 mil PDIP package
DESCRIPTION
The Simtek STK20C04 is a fast static RAM (30, 35,
45ns), with a nonvolatile electrically-erasable PROM
(EEPROM) element incorporated in each static memory
cell. The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in EEPROM. Data may easily be transferred
from the SRAM to the EEPROM (STORE), or from the
EEPROM to the SRAM (RECALL) using the NE pin. It
combines the high performance and ease of use of a
fast SRAM with nonvolatile data integrity.
The STK20C04 features the industry standard pinout
for nonvolatile RAMs in a 28-pin 600 mil plastic DIP.
LOGIC BLOCK DIAGRAM
EEPROM ARRAY
64 X 64
STORE
A3
A4
STATIC RAM
RECALL
A5 ARRAY
A6 64 X 64
A7
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DECODER
A0 A1
A2
PIN CONFIGURATIONS
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
DQ 0
DQ 1
DO 2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 W
26 NC
25 A 8
24 NC
23 NC
22 G
21 NC
20 E
19 DQ 7
18 DQ 6
17 DQ 5
16 DQ 4
15 DQ 3
28 - 600 PDIP
STORE/
RECALL
CONTROL
G
NE
E
W
PIN NAMES
A0 - A8
W
Address Inputs
Write Enable
DQ0 - DQ7
E
Data In/Out
Chip Enable
G Output Enable
NE Nonvolatile Enable
VCC Power (+5V)
VSS Ground
2-39




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STK20C04 Datasheet Preview

STK20C04 Datasheet

CMOS nvSRAM High Performance 512 x 8 Nonvolatile Static RAM

No Preview Available !

STK20C04
ABSOLUTE MAXIMUM RATINGSa
Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
(One output at a time, one second duration)
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
DC CHARACTERISTICS
SYMBOL
ICC1 b
PARAMETER
Average VCC Current
ICC2 d
ISB1c
Average VCC Current
during STORE cycle
Average VCC Current
(Standby, Cycling TTL Input Levels)
ISB2c
IILK
IOLK
VIH
VIL
VOH
VOL
TA
Average VCC Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current (Any Input)
Off State Output Leakage Current
Input Logic "1" Voltage
Input Logic "0" Voltage
Output Logic "1" Voltage
Output Logic "0" Voltage
Operating Temperature
COMMERCIAL
MIN MAX
80
75
65
50
INDUSTRIAL
MIN MAX
85
80
75
50
UNITS
mA
mA
mA
mA
27 30 mA
23 27 mA
20 23 mA
1 1 mA
±1 ±1 µA
±5 ±5 µA
2.2
VSS–.5
2.4
0
VCC+.5
0.8
0.4
70
2.2
VSS–.5
2.4
–40
VCC+.5
0.8
0.4
85
V
V
V
V
°C
(VCC = 5.0V ± 10%)
NOTES
tAVAV = 30ns
tAVAV = 35ns
tAVAV = 45ns
All inputs at
VIN 0.2V or (VCC – 0.2V)
tAVAV = 30ns
tAVAV = 35ns
tAVAV = 45ns
E VIH; all others cycling
E (VCC – 0.2V)
all others VIN 0.2V or (VCC – 0.2V)
VCC = max
VIN = VSS to VCC
VCC = max
VIN = VSS to VCC
All Inputs
All Inputs
IOUT = –4mA
IOUT = 8mA
Note b: ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: ICC2 is the average current required for the duration of the store cycle (tSTORE) after the sequence (tWC) that initiates the cycle.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCE (TA=25°C, f=1.0MHz)e
SYMBOL
PARAMETER
MAX UNITS CONDITIONS
CIN
COUT
Input Capacitance
Output Capacitance & W
7
7
pF V = 0 to 3V
pF V = 0 to 3V
Note e: These parameters are guaranteed but not tested.
2-40
Output
255 Ohms
5.0V
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
Figure 1: AC Output Loading


Part Number STK20C04
Description CMOS nvSRAM High Performance 512 x 8 Nonvolatile Static RAM
Maker ETC
Total Page 8 Pages
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