S5933QE
Description
: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasasserts FRAME# on the next clock to indicate the last data phase is in progress. If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been dasserted. Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this event from occuring. Request separate D8 applications note from your local FAE for more detail. Status: No Factory D8 alteration planned.
D14.1:
False Add-On to PCI FIFO Empty Indication
Description
: If the last data in the Add-On to PCI FIFO is written by the S5933 to the PCI bus and receives a target retry, the FWE output and Add-On to PCI FIFO status bits will go active, indicating that the FIFO is empty, even though the final data has not yet been transferred. This is only a...
