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PEEL18CV8SI-5 - CMOS Programmable Electrically Erasable Logic Device

Download the PEEL18CV8SI-5 datasheet PDF (PEE included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for cmos programmable electrically erasable logic device.

Description

The PEEL18CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs.

The PEEL18CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today.

Features

  • s Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development / Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer - PLD-to-PEEL JEDEC file translator s Architectura.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PEE-L18CV.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PEEL18CV8SI-5
Manufacturer Unknown Manufacturer
File Size 411.95 KB
Description CMOS Programmable Electrically Erasable Logic Device
Datasheet download datasheet PEEL18CV8SI-5 Datasheet

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Full PDF Text Transcription

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® International CMOS Technology Commercial/ Industrial PEEL™ 18CV8 -5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device Features s Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development / Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer - PLD-to-PEEL JEDEC file translator s Architectural Flexibility - Enhanced architecture fits in more logic - 74 product terms x 36 input AND array - 10 inputs and 8 I/O pins - 12 possible macrocell co
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