BJ8P64N Datasheet, ETC

CPU configuration z 2K*14 bits on-chip ROM z 80*8 bits on-chip registers (SRAM) z 8-level stacks for subroutine nesting z Less than 1.9 mA at 5V/4MHz z Typically 15uA, at.

The BJ8P64N is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. The device has an on-chip 2K*14-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent int.