AR2010 - GPS Controller SoC

Datasheet Details

The AR2010 controller SoC includes the following functions and capabilities: CPU: MIPS 1 class R3000 level, 32-bit RISC processor with 2 KB Instruction cache and 2 KB data cache, and up to 100 MHz CPU Clock rate Built-in 64 KB SRAM SDRAM Controller supports two SDRAM banks of 16-bit data bus Up to 32 MB address space GPS Base-band decoder with 12 channel correlators and built-in carrier/code tracking loops LCD display interface driver ADC with touch screen interface controller Supports GPIOs fo.

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Published: Aug 13, 2008 |