M55D4G32128A-CDBG2R sdram equivalent, 16m x 32 bit x 8 banks lpddr3 sdram.
Ball Name
Type
CK_t, CK_c
Input
CKE
Input
CS_n CA[n:0] DQ[n:0]
Input Input I/O
DQS[n:0]_t, I/O
DQS[n:0]_c
DM[n:0]
Input
ODT
Input
M55D4G32128A (2R)
Function Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR).
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Manufacturer
Related datasheet
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