• Part: M15T2G8256A
  • Description: 32M x 8 Bit x 8 Banks DDR3 SDRAM
  • Manufacturer: Elite Semiconductor Microelectronics Technology
  • Size: 3.83 MB
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Elite Semiconductor Microelectronics Technology
M15T2G8256A
M15T2G8256A is 32M x 8 Bit x 8 Banks DDR3 SDRAM manufactured by Elite Semiconductor Microelectronics Technology.
Feature - Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) ˗ SSTL_135: VDD/VDDQ = 1.35V(-0.067V/+0.1V) - JEDEC DDR3(L) pliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM - Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes - Power Saving Mode ˗ Power Down Mode - Signal Integrity ˗ Configurable DS for system patibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) M15T2G8256A (2L) 32M x 8 Bit x 8 Banks DDR3(L) SDRAM - Signal Synchronization ˗ Write Leveling via MR settings ˗ Read Leveling via MPR - Programmable Functions ˗ CAS Latency (5/6/7/8/9/10/11/13) ˗ CAS Write Latency (5/6/7/8/9) ˗ Additive Latency (0/CL-1/CL-2) ˗ Write Recovery Time (5/6/7/8/10/12/14/16) ˗ Burst Type (Sequential/Interleaved) ˗ Burst Length (BL8/BC4/BC4 or 8 on the fly) ˗ Self Refresh Temperature Range(Normal/Extended) ˗ Output Driver Impedance (34/40) ˗ On-Die Termination of Rtt_Nom(20/30/40/60/120) ˗ On-Die Termination of Rtt_WR(60/120) ˗ Precharge Power Down (slow/fast) Note: 1. Only Support prime DQ’s feedback for each byte lane. Ordering Information Product ID M15T2G8256A- DEBG2L M15T2G8256A- BDBG2L Max Freq. VDD Data Rate (CL-t RCD-t RP) Package 933MHz 1.35/ 1.5V DDR3(L)-1866 (13-13-13) 800MHz 1.35/ 1.5V DDR3(L)-1600 (11-11-11) 78 ball BGA ments Pb-free Pb-free Elite Semiconductor Memory Technology Inc Publication Date : Aug. 2018 Revision : 1.0 1/140 ESMT M15T2G8256A (2L) Description The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications. The chip is designed to ply with...