M15T2G8256A sdram equivalent, ddr3 sdram.
and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential c.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are syn.
The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 bank devices. These synchronous device.
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