M15F2G16128A-EFBG2LS sdram equivalent, ddr3 sdram.
and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential c.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchr.
The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices ach.
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