Datasheet Summary
ESMT
DR3 SDRAM
Feature
- Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)
- JEDEC DDR3 pliant ˗ 8n Prefetch Architecture ˗ Differential Clock (CK/ CK ) and Data Strobe (DQS/ DQS ) ˗ Double-data rate on DQs, DQS and DM
- Data Integrity ˗ Auto Self Refresh (ASR) by DRAM built-in TS ˗ Auto Refresh and Self Refresh Modes
- Power Saving Mode ˗ Power Down Mode
- Signal Integrity ˗ Configurable DS for system patibility ˗ Configurable On-Die Termination ˗ ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
M15F2G16128A (2L)
16M x 16 Bit x 8 Banks DDR3 SDRAM
- Signal Synchronization
˗ Write Leveling via MR settings ˗ Read Leveling via MPR
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