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M15F2G16128A-DEBG2LS - 16M x 16 Bit x 8 Banks DDR3 SDRAM

Download the M15F2G16128A-DEBG2LS datasheet PDF. This datasheet also covers the M15F2G16128A-EFBG2L variant, as both devices belong to the same 16m x 16 bit x 8 banks ddr3 sdram family and are provided as variant models within a single manufacturer datasheet.

Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.

Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. DDR3 SDRAM Addressing Configuration 128Mb x16 # of Bank 8 Bank Address BA0.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M15F2G16128A-EFBG2L-ESMT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M15F2G16128A-DEBG2LS
Manufacturer ESMT
File Size 3.70 MB
Description 16M x 16 Bit x 8 Banks DDR3 SDRAM
Datasheet download datasheet M15F2G16128A-DEBG2LS Datasheet

Full PDF Text Transcription

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ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.
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